We put a tester in the size of a postcard

MEMS Device-Oriented Tester

Key Features


  • Cost per pin < 100 USD
  • Dedicated CPU per DUT
  • Single card with all A/D resources to test a DUT
  • Up to 1,152 Analog/Digital channels
  • Integration into MEMS stimulus, hard/soft docking with handler/prober, benchtop use

MEMS Device-Oriented Testers
We put a tester in the size of a postcard


Are your test requirements oriented to defined families of devices, with common characteristics? You do not need to purchase an expensive, general-purpose mixed signal tester: You can rely on SPEA DOT 100, a system designed to answer the test requirements of MEMS and other low-pin-count devices at an incredibly low cost.

The DOT 100 is based on a revolutionary per-device architecture: each device under test has a dedicated CPU managing the entire test process, while each card hosts all the resources for the parallel test of 6 devices, in the size of a postcard.

All this is contained in a hand-carryable size, which can be integrated in the SPEA MEMS stimulus, hard/soft docked with prober or handler, or used as benchtop unit.

Multi-site fast parallel test

  • dedicated CPU per device
  • up to 1,152 Analog/Digital channels
  • device power supply and time measurement unit per device
  • pattern memory per channel (30 Mstep)
  • asynchronous digital capabilities
  • programmable logic units (SPI, I2Cbus, Uart, IO Port)

Ultra high density pin electronics

At the core of DOT testers is the pin electronics, which provides 48/96 channels in 3/6 independent sections.

Each section contains:

  • 8 digital channels @5MHz & 8 analog channels (DPS) up to 10V; 256mA  (driver and digitizer per pin)
  • 8 digital channels @50MHz + 1 analog channel  (driver and digitizer multiplexed)
  • 2 time measurement units

Full parallel final test concept

SPEA test cells perform the complete parametric and functional test on the fully packaged devices, at the end of the production process.

After the test, the products can be directly shipped to the customer, without needing any further working or re-test.

Test Program Generation & Debug < 1 day


  • Easy-to-learn programming environment
  • Guided Test Program generation
  • The Automatic code generation dramatically shortens the time taken to develop, debug and release the program
  • Automatic data import
  • DUT-Oriented & Instrument-Oriented instruction Libraries
  • DUT Map
  • Very Rapid Application Development
  • Test Result Analyzer
  • Shmoo Plot
  • Easy to run. Easy to monitor. Easy to maintain.
Design & Code by dsweb.lab